The inventive concepts described herein relate to a duty cycle correcting device, a duty cycle correcting method, and a receiver using the duty cycle correcting device and method.
Like a clock signal, a pulse signal having a plurality of pulses may have a predetermined duty cycle. The duty cycle may indicate a ratio of a pulse width to a pulse period, and a measure may be designated by “%”.
A duty cycle corrector to correct a duty cycle may be applied to a delay locked loop (DLL) or a phase locked loop (PLL) such that a duty cycle of an output clock signal maintains a predetermined value (e.g., 50%).
The duty cycle corrector may store information on a duty error (e.g., indicating a level by which a duty cycle gets out of a desired duty cycle), and may correct the duty error of a clock signal using the stored information.
A conventional duty cycle corrector may correct only a duty of a clock signal where a pulse is repeated periodically. The conventional duty cycle corrector may not correct a duty cycle of a data signal for transferring data in a digital manner using a pulse. For this reason, a range of the conventional duty cycle corrector may be limited.